1. Field of the Invention
This invention relates to a data interface that receives data signals and aligns those signals at an optimal sample location between clock edges of a sampling clock. The data interface can be included within a network communication system and, more particularly, within a packet framer or packet mapper to receive transmitted data from link layer devices of a node or communication network, and for aligning the transmitted data within bit locations of the frame defined by the edges of the sampling clock.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
In order to successfully implement a synchronous system, it is beneficial to properly align a sampling clock to the data being sampled. This entails making sure that if a data transition is to be sampled, the data transition occurs at the proper moment between clock edges or transitions. Synchronous circuits therefore rely on the data transitioning and remaining stable from at least a “set-up” time before the clock transitions until at least a “hold time” after the clock transitions.
Most synchronous systems have significant set-up and hold time requirements. As the clock transition frequency increases, the margin of time in which data can transition between the set-up and hold times decreases proportionally. High speed synchronous systems can ill-afford significant skewing or jitter of the clocking signal relative to data signal transitions.
In addition to clock signal skewing and jitter problems, many clocks also experience duty cycle fluctuations. For example, a clocking signal which has a longer duration positive pulse than its negative pulse will cause an irregular data signal sampling if data is sampled at each transition of the clocking signal. Most high-speed synchronous systems will use both edges of the clocking signal to sample data or possibly multiple phases of those edges. If the positive pulse is less than the negative pulse (or vice-versa), then the sampling margin for data transitions will be different between successive pairs of clock edges.
Although numerous techniques are used in an effort to minimize skewing, jitter, and duty cycle fluctuations, most techniques cannot in all conditions ensure data signal transitions occur in the critical sampling margin, or range. For example, in the case where data signals might be those sent across a communication system or network, the clock signal could possibly be recovered from the data signal and therefore suffer the same skewing and jitter problems of the data signal.
The problem of adjusting skew is sometimes addressed by generating delayed versions of the clock signal and selecting an appropriate phase that is most appropriate to sample the data. A retiming circuit is therefore needed, which involves possibly analog circuit and a relatively large consumption of power. While the problem is generally prevalent in all synchronously controlled subsystems, it can arise in communication systems that rely on synchronous operation/sampling. Regardless of the application, synchronous systems (or synchronous systems in a communication system setting) employ a data interface. The data interface optimally receives transmitted data properly timed with respect to a clocking signal. The transmitted data can be sent from, for example, a processor attributed to a node or possibly from another processor separated from the data interface (e.g., framer within a communication system) by a network transmission link. In a communication system example, the Optical Internetworking Forum (“OIF”) recognized the data skewing problem and specified the operation of a communication system framer at the receive port of the framer by defining a system packet interface (“SPI”) de-skewing mechanism. For example, SPI can define a packet-over-SONET (“POS”) physical device that receives transmitted data into the SPI of the SONET framer. The SPI-4 OIF agreement allows for a skew between the data and clock signals for as much as plus or minus one cycle of the clock signal.
A mechanism is thereby needed which can detect skewing within one half clock cycle (within one bit location) and can essentially de-skew the sub-bit skew. The desired mechanism should, therefore, be able to essentially move a data transition away from the clock edges and optimally near a midpoint between clock transitions. The mechanism should be one that can be used as a flexible interface, which can be adjusted manually or programmably when deemed necessary. This will allow the data to be sampled well within the optimal sampling margins. The desired de-skew interface or de-skew mechanism should be applicable to any synchronous system, including a synchronous system used in communication system for transferring packets of data between nodes, such systems include gateways, routers, computer workstations, switches, and/or general multimedia devices which rely upon accurate framing and de-framing of synchronous data.